Charge coupled device

ABSTRACT

Embodiments of a system and method for generating a pixel value use at least a first pixel in a first row of a charge coupled device (CCD) and a first pixel in a second row, adjacent to the first row, of the CCD.

BACKGROUND

An image capture device may capture a digital image by detecting photonsreceived by a charge coupled device (CCD) or other photosensor arrayover a time period.

The time period used to expose a pixel of a CCD array to light from themedium often depends on the size of the pixels being exposed. Generally,larger pixels capture greater numbers of photons in a given time periodthan do smaller pixels, i.e., larger pixels may have a highersensitivity than smaller pixels. As a result, CCD arrays with largerpixels may operate faster than CCD arrays with smaller pixels.Unfortunately, larger pixels also increase the size of a CCD array. Anincrease in size of the CCD array may increase the cost of the array. Asa result, CCD arrays with relatively large pixels that provide higherspeed performance may be more expensive than CCD arrays with relativelysmall pixels that provide lower speed performance.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram illustrating an embodiment of a multi-functiondevice according to one embodiment of the present disclosure.

FIG. 2 is a block diagram illustrating an embodiment of a scanner withan embodiment of a multiple mode linear CCD array according to oneembodiment of the present disclosure.

FIG. 3 is a schematic diagram illustrating an embodiment of a multiplemode linear CCD array according to one embodiment of the presentdisclosure.

FIG. 4 is a flow chart illustrating an embodiment of a method forcapturing an image using an embodiment of a multiple mode linear CCDarray according to one embodiment of the present disclosure.

FIG. 5 is a schematic diagram illustrating capturing pixel values for animage in a first mode of operation of an embodiment of a linear CCDarray according to one embodiment of the present disclosure.

FIG. 6 is a timing diagram illustrating capturing a pixel value for animage in a first mode of operation of an embodiment of a linear CCDarray according to one embodiment of the present disclosure.

FIG. 7 is a schematic diagram illustrating capturing pixel values for animage in a second mode of operation of an embodiment of a linear CCDarray according to one embodiment of the present disclosure.

FIG. 8 is a timing diagram illustrating capturing a pixel value for animage in a second mode of operation of an embodiment of a linear CCDarray according to one embodiment of the present disclosure.

FIG. 9 is a schematic diagram illustrating capturing pixel values for animage in a third mode of operation of an embodiment of a linear CCDarray according to one embodiment of the present disclosure.

FIG. 10 is a timing diagram illustrating capturing a pixel value for animage in a third mode of operation of an embodiment of a linear CCDarray according to one embodiment of the present disclosure.

FIG. 11 is a schematic diagram illustrating capturing pixel values foran image in a fourth mode of operation of an embodiment of a linear CCDarray according to one embodiment of the present disclosure.

FIG. 12 is a timing diagram illustrating capturing a pixel value for animage in a fourth mode of operation of an embodiment of a linear CCDarray according to one embodiment of the present disclosure.

DETAILED DESCRIPTION

In the following detailed description, reference is made to theaccompanying drawings, which form a part hereof, and in which is shownby way of illustration specific embodiments in which the disclosedsubject matter may be practiced. It is to be understood that otherembodiments may be utilized and structural or logical changes may bemade without departing from the scope of the present disclosure. Thefollowing detailed description, therefore, is not to be taken in alimiting sense, and the scope of the present disclosure is defined bythe appended claims.

As described herein, an embodiment of a charge coupled device, such as amultiple mode linear CCD array, is provided. The multiple mode linearCCD array may be operated in different resolution modes to acquire adigital image from a medium. In one or more of the resolution modes, thedigital image is acquired by merging pixel values from different pixelsto create the pixel values of the digital image. The merged pixel valuesmay comprise multiple pixel values from pixels in the same row andmultiple pixel values from pixels in a different row. In otherresolution modes, the digital image is acquired by detecting a separatepixel value from each of a set of pixels. The set of pixels may compriseone or more rows of pixels in the linear CCD array.

FIG. 1 is a block diagram illustrating one embodiment of amulti-function device 100. Multi-function device 100 comprises a controlunit 102, a scanner 104, a printer 106, and a facsimile device 108.Control unit 102 comprises an interface 110, a processor 112, andfirmware 114.

Control unit 102 controls and manages the operation of scanner 104,printer 106, and facsimile device 108 in response to informationreceived from an input/output device (not shown) or an external device(not shown) coupled, directly or indirectly, to interface 110. Theinput/output device may include any combination of buttons, keys, dials,switches, touch-pads, and visual displays, for example. The externaldevice may be a computer system or a print server, for example.Processor 112 executes instructions in firmware 114 to process thesignals received from the input/output device and from interface 110 andcontrol and manage the operation of scanner 104, printer 106, andfacsimile device 108. Firmware 114 may be stored in any suitable storagemedium accessible by processor 112. In addition, firmware 114 may bestored externally to multi-function device 100 prior to being storedinternally to multi-function device 100.

Printer 106 comprises any type of impact or non-impact printing deviceconfigured to transfer text and/or images to paper or another type ofmedia. Types of printing devices include laser printers, inkjetprinters, bubble jet printers, thermal printers, and plotters. Printer106 receives text and/or images from an external device and prints thetext and/or images onto a media, e.g., paper, from one or more mediatrays (not shown).

Scanner 104 is configured to scan images from a medium into anelectronic format and perform processing on the scanned images.Additional details of scanner 104 will be described below with referenceto FIGS. 2-10.

Facsimile device 108 is configured to send and receive electronic imagesusing a network connection, e.g., a telephone line or an Internetconnection (not shown). Facsimile device 108 acquires an electronicimage from a medium using scanner 104 and sends the electronic image toanother facsimile or other device using the network connection. Inresponse to receiving an electronic image from the network connection,facsimile device 108 causes printer 106 to print the electronic imageonto a medium.

FIG. 2 is a block diagram illustrating one embodiment of scanner 104with a multiple mode linear charge coupled device (CCD) array 206.Scanner 104 comprises a control unit 202, a drive mechanism 204, linearCCD array 206, an illumination source 208, and a memory 212.

Scanner 104 communicates with multi-function device 100 using interface214. More particularly, control unit 202 of scanner 104 receives acommand from control unit 102 in multi-function device 100 to capture animage from a medium 220. Control unit 202 may also receive parametersassociated with the command that indicate a resolution mode or othermode of operation with which to capture the image. In response toreceiving the command, control unit 202 provides control signals todrive mechanism 204, linear CCD array 206, illumination source 208, andmemory 212 to cause the image to be captured from medium 220.

Control unit 202 may comprise any suitable combination of hardware andsoftware components configured to perform the functions describedherein. For example, control unit 202 may comprise firmware (not shown)that is executed by a processor (not shown) wherein the firmware isstored in any suitable storage medium accessible by the processor. Thefirmware may be stored externally to scanner 104 prior to being storedinternally to scanner 104.

Responsive to control signals from control unit 202, drive mechanism 204either moves linear CCD array 206 relative to medium 220 as indicated byan arrow 216A or moves medium 220 relative to linear CCD array 206 asindicated by an arrow 216B to allow regions of medium 220 to be exposedto linear CCD array 206 during an exposure period. During the exposureperiod, light from illumination source 208 is reflected off of ortransmitted through medium 220 and onto linear CCD array 206. The pixelsin linear CCD array 206 capture photons to allow raw pixel valuesassociated with the captured photons to be read out of linear CCD array206 and stored in memory 212. The raw pixel values are processed orconverted into pixel values that comprise a digital image of medium 220.

FIG. 3 is a schematic diagram illustrating one embodiment of multiplemode linear CCD array 206. Linear CCD array 206 comprises a set of rows302B with pixels 304B configured for receiving a first color, e.g.,blue, a set of rows 302G with pixels 304G configured for receiving asecond color, e.g., green, and a set of rows 302R with pixels 304Rconfigured for receiving a third color, e.g., red. In the embodiment ofFIG. 3, each set of rows 302B, 302G, and 302R comprises four rows, i.e.,rows B1 through B4, rows G1 through G4, and rows R1 through R4,respectively. In other embodiments, each set of rows 302B, 302G, and302R may comprise other numbers of rows greater than or equal to two.

Linear CCD array 206 comprises CCD shift registers 306B and 308B for theset of rows 302B, CCD shift registers 306G and 308G for the set of rows302G, and CCD shift registers 306R and 308R for the set of rows 302R. Inthe set of rows 302B, gate logic 310B and 312B comprise circuitry tocontrol the shifting of charge from row B2 to CCD shift register 306Band from row B1 to CCD shift register 306B, respectively, and gate logic314B and 316B comprise circuitry to control the shifting of charge fromrow B3 to CCD shift register 308B and from row B4 to CCD shift register308B, respectively. Gate logic 310G, 312G, 314G, and 316G functionsimilarly for the set of rows 302G, and gate logic 310R, 312R, 314R, and316R function similarly for the set of rows 302R. Linear CCD array 206also comprises control logic interspersed between the sets of rows 302B,302G, and 302R.

Linear CCD array 206 further comprises output nodes 318B, 318G, and 318Rfor sets of rows 302B, 302G, and 302R, respectively. After charge isstored in shift registers 306B and 308B, the charge for each pixel 304Bis shifted serially from shift registers 306B and 308B into output node318B. Depending on the mode of operation, charge from shift registers306B and 308B may be alternately shifted during different portions of aclock cycle. Output nodes 318G and 318R function similarly for the setsof rows 302G and 302R, respectively.

Each row in sets of rows 302B, 302G, and 302R has a set pixelresolution, e.g., 1200 dots per inch, in the direction parallel to therow, i.e., the x direction. In addition, the rows of each set of rows302B, 302G, and 302R are offset from one another in the directionparallel to the rows. For example, row B2 is offset from row B3 by adistance equal to one-half of a width of a pixel 304B in the positive xdirection as indicated by an arrow 322 in set of rows 302B. Row B1 isoffset from row B2 by a distance equal to one-fourth of a width of apixel 304B in the positive x direction as indicated by an arrow 326 inset of rows 302B. Row B4 is offset from row B3 by a distance equal toone-fourth of a width of a pixel 304B in the positive x direction asindicated by an arrow 324 in set of rows 302B. Sets of rows 302G and302R are similarly configured. In other embodiments, other offsetdistances between the various rows in sets of rows 302B, 302G, and 302Rmay be used.

Linear CCD array 206 may be operated in different resolution modes toacquire a digital image from medium 220. In one or more of theresolution modes, the digital image is acquired by merging pixel valuesfrom different pixels 304 to create the pixel values of the digitalimage. The merged pixel values may comprise multiple pixel values frompixels 304 in the same row from sets of rows 302B, 302G, and 302R andmultiple pixel values from pixels 304 in a different row from sets ofrows 302B, 302G, and 302R. In other resolution modes, the digital imageis acquired by detecting a separate pixel value from each of a set ofpixels 304. The set of pixels 304 may comprise one or more rows of setsof rows 302B, 302G, and 302R of pixels 304 in the linear CCD array.

FIG. 4 is a flow chart illustrating one embodiment of a method forcapturing an image using the various resolution modes of operation,i.e., resolution modes, of linear CCD array 206. The resolution modesreferenced in the embodiment of FIG. 4 will be illustrated withreference to the embodiments of FIGS. 5-10. In the embodiment of FIG. 4,a determination is made by scanner 104 as to whether an image captureprocess has been initiated as indicated in a block 400. An image captureprocess may be initiated in response to scanner 104 receiving a commandor other signal from multi-function device 100 that indicates an imagecapture is to be performed.

Once an image capture process has been initiated, scanner 104 detects amode of operation associated with the image capture as indicated in ablock 402. In one embodiment, scanner 104 detects the mode of operationfrom a parameter or other signal received from multi-function device 100that indicates the mode of operation. In other embodiments, scanner 104detects the mode of operation by accessing information stored in memory212 or another memory (not shown) that indicates the mode of operation.

A determination is made by scanner 104 as to whether the mode operationis a low resolution mode as indicated in a block 404. If the modeoperation is a low resolution mode, then scanner 104 captures the imagefrom medium 220 by merging pixel values from adjacent pixels from onerow with pixel values from adjacent pixels from an adjacent row for eachcolor to generate the digital image pixel values as indicated in a block406. The function of block 406 is illustrated in FIGS. 5 and 6.

FIG. 5 is a schematic diagram illustrating one embodiment of capturingpixel values for an image in a first mode, i.e., low resolution mode, ofoperation of linear CCD array 206. As illustrated in the embodiment ofFIG. 5, linear CCD array 206 merges two pixel values from adjacentpixels 304 from one row with two pixel values from adjacent pixels 304from an adjacent row for each color using shift registers 306 and 308and output node 318. More particularly, linear CCD array 206 merges twopixel values from adjacent pixels 304B in row B2 with two pixel valuesfrom adjacent pixels 304B in row B3 to generate a single pixel value502B of a first color, i.e., blue. Similarly, linear CCD array 206merges two pixel values from adjacent pixels 304G in row G2 with twopixel values from adjacent pixels 304G in row G3 to generate a singlepixel value 502G of a second color, i.e., green. Further, linear CCDarray 206 merges two pixel values from adjacent pixels 304R in row R2with two pixel values from adjacent pixels 304R in row R3 to generate asingle pixel value 502R of a third color, i.e., red.

FIG. 6 is a timing diagram illustrating one embodiment of capturing apixel value for an image in the low resolution mode of operation oflinear CCD array 206. The timing diagram illustrates a clock signal, adata out signal, a reset signal, a dark sample signal, and a videosample signal of linear CCD array 206.

During a clock pulse, control unit 202 asserts the reset signal to causeoutput node 318B in linear CCD array 206 to be cleared. As a result, thedata out signal transitions to a first, or reset, level. Control unit202 asserts the dark sample signal after the reset signal to cause thefirst level of output node 318B to be stored as a dark sample forcomparison.

On the clock edge following the dark sample signal, control unit 202causes charge corresponding to the pixel value for the nth pixel in rowB2, i.e., pixel B2[n] where n is a whole odd number, to be transferredto output node 318B to cause the data out signal to change to a secondlevel. On the next clock edge, control unit 202 causes chargecorresponding to the pixel value for the nth pixel in row B3, i.e.,pixel B3[n], to be transferred to output node 318B to cause the data outsignal to change to a third level such that the third level representsthe merged sum of the pixel values for pixels B2[n] and B3[n]. As shownin the embodiment of FIG. 3, row B2 is adjacent to row B3. Pixels B2[n]and B3[n] are also adjacent, but offset by one-half of a width of apixel 304B.

On the next clock edge, control unit 202 causes charge corresponding tothe pixel value for the (n+1)th pixel in row B2, i.e., pixel B2[n+1], tobe transferred to output node 318B to cause the data out signal tochange to a fourth level such that the fourth level represents themerged sum of the pixel values for pixels B2[n], B3[n], and B2[n+1].Pixel B2[n+1] is adjacent to pixel B2[n] in row B2. On the next clockedge, control unit 202 causes charge corresponding to the pixel valuefor the (n+1)th pixel in row B3, i.e., pixel B3[n+1], to be transferredto output node 318B to cause the data out signal to change to a fifthlevel such that the fifth level represents the merged sum of the pixelvalues for pixels B2[n], B3[n], B2[n+1], and B3[n+1]. Pixel B3[n+1] isadjacent to pixel B3[n] in row B2.

During the clock cycle in which the data out signal is at the fifthlevel, control unit 202 asserts the video sample signal to cause thedata out signal to be compared to the dark sample to generate a pixelvalue 502B associated with the four merged pixels B2[n], B3[n], B2[n+1],and B3[n+1]. The pixel value 502B is stored in memory 212.

Each pixel value 502B for the remaining pixels 304B in rows B2 and B3 isgenerated sequentially as just described. In addition, the pixel values502G and 502R for the pixels 304G in rows G2 and G3 and the pixels 304Rin rows R2 and R3, respectively, are generated in parallel withgenerating the pixel values 502B.

In other embodiments, the low resolution mode may be implemented bycombining other numbers of pixels from rows B2 and B3. For example, fourpixels from row B2 may be combined with four pixels from row B3 togenerate pixel value 502B. As another example, one pixel from row B2 maybe combined with one pixel from row B3 to generate pixel value 502B.

Returning to the embodiment of FIG. 4, if the mode operation is not alow resolution mode, then a determination is made by scanner 104 as towhether the mode operation is a medium resolution mode as indicated in ablock 408. If the mode operation is a medium resolution mode, thenscanner 104 captures the image from medium 220 using individual pixelsin one row for each color as indicated in a block 410. The function ofblock 410 is illustrated in the embodiments of FIGS. 7 and 8.

FIG. 7 is a schematic diagram illustrating one embodiment of capturingpixel values for an image in a second mode, i.e., medium resolutionmode, of operation of linear CCD array 206. As illustrated in theembodiment of FIG. 7, linear CCD array 206 generates pixel values 702B,702G, and 702R for the digital image from individual pixels in rows B2,G2, and R2, respectively. In other embodiments, another row in each setof rows 302B, 302G, and 302R may be used, e.g., rows B1, G1, and R1.

FIG. 8 is a timing diagram illustrating one embodiment of capturingpixel values for an image in the medium resolution mode of operation oflinear CCD array 206. The timing diagram illustrates a clock signal, adata out signal, a reset signal, a dark sample signal, and a videosample signal of linear CCD array 206. During the rising clock edge,control unit 202 asserts the reset signal to cause output node 318B inlinear CCD array 206 to be cleared. As a result, the data out signaltransitions to a first or dark level. Control unit 202 asserts the darksample signal after the reset signal to cause the first level to bestored as a dark sample for comparison.

On the falling clock edge following the dark sample signal, control unit202 causes charge corresponding to pixel value for a pixel in row B2,i.e., pixel B2[n] where n is a whole number, to be transferred to outputnode 318 to cause the data out signal to change to a second level.Control unit 202 asserts the video sample signal while the data outsignal is at the second level to cause the data out signal to becompared to the dark sample to generate a pixel value 702B associatedwith the pixel B2[n]. The pixel value 702B is stored in memory 212.

On the next rising clock edge, the reset and dark sample signals areasserted as described above. On the falling clock edge following thedark sample signal, control unit 202 causes charge corresponding topixel value for a next pixel in row B2, i.e., pixel B2[n+1] where n is awhole number, to be transferred to output node 318 to cause the data outsignal to be changed to a third level. Control unit 202 asserts thevideo sample signal while the data out signal is at the third levelcause the data out signal to be compared to the dark sample to generatea pixel value 702B associated with the pixel B2[n+1]. The pixel value702B is stored in memory 212.

The process repeats for each pixel in row B2. The pixel values 702G and702R for the pixels 304G in row G2 and the pixels 304R in row R2,respectively, are generated in parallel with generating the pixel values702B as just described.

Returning to the embodiment of FIG. 4, if the mode operation is not amedium resolution mode, then a determination is made by scanner 104 asto whether the mode operation is a high resolution mode as indicated ina block 412. If the mode operation is a high resolution mode, thenscanner 104 captures the image from medium 220 using individual pixelsin two rows for each color as indicated in a block 414. The function ofblock 414 is illustrated in the embodiments of FIGS. 9 and 10.

FIG. 9 is a schematic diagram illustrating one embodiment of capturingpixel values for an image in a third mode, i.e., high resolution mode,of operation of linear CCD array 206. As illustrated in the embodimentof FIG. 9, linear CCD array 206 generates pixel values 902B, 902G, and902R for the digital image from individual pixels in rows B2 and B3, G2and G3, and R2 and R3, respectively. In other embodiments, another setof two rows from each set of rows 302B, 302G, and 302R may be used,e.g., rows B1 and B4, G1 and G4, and R1 and R4.

FIG. 10 is a timing diagram illustrating one embodiment of capturingpixel values for an image in the high resolution mode of operation oflinear CCD array 206. The timing diagram illustrates a clock signal, adata out signal, a reset signal, a dark sample signal, and a videosample signal of linear CCD array 206. During a clock pulse, controlunit 202 asserts the reset signal to cause output node 318B in linearCCD array 206 to be cleared. As a result, the data out signaltransitions to a first or dark level. Control unit 202 asserts the darksample signal after the reset signal to cause the first level to bestored as a dark sample for comparison.

On the clock edge following the dark sample signal, control unit 202causes charge corresponding to pixel value for a pixel in row B2, i.e.,pixel B2[n] where n is a whole number, to be transferred to output node318 to cause the data out signal to change to a second level. Controlunit 202 asserts the video sample signal while the data out signal is atthe second level to cause the data out signal to be compared to the darksample to generate a pixel value 902B associated with the pixel B2[n].The pixel value 902B is stored in memory 212.

Subsequent to the video sample signal, the reset and dark sample signalsare asserted as described above. On the clock edge following the darksample signal, control unit 202 causes charge corresponding to pixelvalue for a pixel in row B3, i.e., pixel B3[n] where n is a wholenumber, to be transferred to output node 318 to cause the data outsignal to be changed to a third level. Control unit 202 asserts thevideo sample signal while the data out signal is at the third levelcause the data out signal to be compared to the dark sample to generatea pixel value 902B associated with the pixel B3[n]. The pixel value 902Bis stored in memory 212.

The process repeats for each pixel in rows B2 and B3, e.g., pixelB2[n+1], B3[n+1], and B2[n+2], etc, as shown in the embodiment of FIG.10. The pixel values 902G and 902R for the pixels 304G in rows G2 and G3and the pixels 304R in rows R2 and R3, respectively, are generated inparallel with generating the pixel values 902B as just described.

In another embodiment, control unit 202 causes the pixel values 902Bfrom rows B2 and B3 to be generated in a sequential manner. In thisembodiment, the pixel values 902B for pixels from row B2 are generatedand the pixel values 902B from row B3 are generated subsequent to thegenerating the pixel values 902B from row B2. The pixel values 902G and902R for the pixels 304G in rows G2 and G3 and the pixels 304R in rowsR2 and R3, respectively, are generated in parallel with generating thepixel values 902B as just described in this alternative embodiment.

Returning to the embodiment of FIG. 4, if the mode operation is not ahigh resolution mode, then a determination is made by scanner 104 as towhether the mode operation is a super resolution mode as indicated in ablock 416. If the mode operation is a super resolution mode, thenscanner 104 captures the image from medium 220 using individual pixelsin four rows for each color as indicated in a block 418. The function ofblock 418 is illustrated in the embodiments of FIGS. 11 and 12.

FIG. 11 is a schematic diagram illustrating one embodiment of capturingpixel values for an image in a fourth mode, i.e., super resolution mode,of operation of linear CCD array 206. As illustrated in the embodimentof FIG. 11, linear CCD array 206 generates pixel values 1102B, 1102G,and 1102R for the digital image from individual pixels in rows B1through B4, G1 through G4, and R1 through R4, respectively.

Control unit 202 generates the signals shown in the embodiments of FIGS.10 and 12 to generate the pixel values for the digital image from theindividual pixels 1102B, 1102G, and 1102R. In one embodiment, controlunit 202 causes the pixel values 1102B from rows B2 and B3 to begenerated in an alternating manner as described above with reference tothe embodiment of FIG. 10 and then causes the pixel values 1102B fromrows B1 and B4 to be generated in an alternating manner as shown in theembodiment of FIG. 12. As shown in FIG. 12, control unit 202 generatespixel values 1102B associated with the pixels B1[n], B4[n], B1[n+1],B4[n+1], B1[n+2], etc., from rows B1 and B4 similar to the way controlunit 202 generates pixel values 902B from rows B2 and B3 as describedabove with reference to the embodiment of FIG. 10. The pixel values1102G and 1102R for the pixels 304G in rows G1 through G4 and the pixels304R in rows R1 through R4, respectively, are generated in parallel withgenerating the pixel values 1102B as just described.

In another embodiment, control unit 202 causes the pixel values 1102Bfrom rows B1 through B4 to be generated in a sequential manner. In thisembodiment, the pixel values 1102B from row B2 are generated subsequentto the generating the pixel values 1102B from row B1, the pixel values1102B from row B3 are generated subsequent to the generating the pixelvalues 1102B from row B2, and pixel values 1102B from row B4 aregenerated subsequent to the generating the pixel values 1102B from rowB3. The pixel values 1102G and 1102R for the pixels 304G in rows G1through G4 and the pixels 304R in rows R1 through R4, respectively, aregenerated in parallel with generating the pixel values 1102B as justdescribed in this embodiment.

In one embodiment, pixels 304B each have a width of 2.7 μm and a heightof 2.7 μm. In this embodiment, row B2 is offset from row B3 by adistance equal to one-half of a width of a pixel 304B, i.e., 1.35 μm, inthe positive x direction, row B1 is offset from row B2 by a distanceequal to one-fourth of a width of a pixel 304B, i.e., 0.675 μm, in thepositive x direction, and row B4 is offset from row B3 by a distanceequal to one-fourth of a width of a pixel 304B, i.e., 0.675 μm, in thepositive x direction. In addition, row B2 is separated from row B3 by adistance of 4.05 μm. Pixels 304G and 304R and sets of rows 302G and 302Rare similarly configured.

In one embodiment, CCD array 206 has a color to color spacing of 64.8 μmfor a total optical width of 194.4 μm. In this embodiment, pixels 304reach saturation at approximately 20,000 electrons. In this embodiment,the sensitivity of pixels 304B ranges between 0.5 and 0.9 V/lux*s with atypical value of approximately 0.7 V/lux*s, the sensitivity of pixels304G ranges between 0.75 and 1.4 V/lux*s with a typical value ofapproximately 1.1 V/lux*s, and the sensitivity of pixels 304R rangesbetween 0.6 and 1.0 V/lux*s with a typical value of approximately 0.8V/lux*s.

In one embodiment, CCD array 206 has a minimum saturation voltage ofapproximately 2.0 V with a typical value of approximately 2.5 V. In thisembodiment, CCD array 206 has approximately 0.1 mV of random noise, anda maximum reset noise voltage of approximately 1.1 V with a typicalvalue of approximately 0.9 V. In addition, CCD array 206 has a maximumdark signal voltage of approximately 2 mV with a typical value ofapproximately 1 mV in this embodiment. Further, CCD array 206 has amaximum DSNU of approximately 7 mV with a typical value of approximately3 mV in this embodiment. CCD array 206 also has a maximum PRNU ofapproximately 20% with a typical value of approximately 10%. CCD array206 has a maximum PRNU(3) of approximately 3 mV with a typical value ofapproximately 12 mV.

Although specific embodiments have been illustrated and described hereinfor purposes of description of the embodiments, it will be appreciatedby those of ordinary skill in the art that a wide variety of alternateand/or equivalent implementations may be substituted for the specificembodiments shown and described without departing from the scope of thepresent disclosure. Those with skill in the art will readily appreciatethat the present disclosure may be implemented in a very wide variety ofembodiments. This application is intended to cover any adaptations orvariations of the disclosed embodiments discussed herein. Therefore, itis manifestly intended that the scope of the present disclosure belimited only by the claims and the equivalents thereof.

1. A system comprising: a charge coupled device (CCD) comprising a first row comprising a first plurality of pixels and a second row adjacent to the first row and comprising a second plurality of pixels; and first circuitry to generate a first pixel value using at least a first one of the first plurality of pixels and a first one of the second plurality of pixels.
 2. The system of claim 1 wherein the first row is offset from the second row in a direction that is parallel to the first and second rows.
 3. The system of claim 2 wherein the first row is offset from the second row by one-half of a width of one of the first plurality of pixels.
 4. The system of claim 2 wherein the first one of the first plurality of pixels is adjacent to the first one of the second plurality of pixels.
 5. The system of claim 1 wherein the first circuitry is to generate the first pixel value using at least the first one of the first plurality of pixels, the first one of the second plurality of pixels, a second one of the first plurality of pixels, and a second one of the second plurality of pixels.
 6. The system of claim 5 wherein the first one of the first plurality of pixels is adjacent to the second one of the first plurality of pixels, and wherein the first one of the second plurality of pixels is adjacent to the second one of the second plurality of pixels.
 7. The system of claim 6 wherein the first one of the first plurality of pixels is adjacent to the first one of the second plurality of pixels, and wherein the second one of the first plurality of pixels is adjacent to the second one of the second plurality of pixels.
 8. The system of claim 7 wherein the first and the second ones of the first plurality of pixels are offset from the first and the second ones of the second plurality of pixels in a direction that is parallel to the first row.
 9. The system of claim 1 wherein the CCD comprises a third row comprising a third plurality of pixels and a fourth row adjacent to the third row and comprising a fourth plurality of pixels, wherein the first and the second pluralities of pixels are associated with a first color, and wherein the third and the fourth pluralities of pixels are associated with a second color, and further comprising: second circuitry to generate a second pixel value using at least one of the third plurality of pixels and one of the fourth plurality of pixels.
 10. The system of claim 9 wherein the first color includes one of blue, green, and red, wherein the second color includes one of blue, green, and red, and wherein the first color differs from the second color.
 11. A method comprising: capturing a first pixel value using at least a first pixel in a first row of a charge coupled device (CCD) and a first pixel in a second row, adjacent to the first row, of the CCD.
 12. The method of claim 11 wherein the first row is offset from the second row in a direction that is parallel to the first and second rows.
 13. The method of claim 12 wherein the first pixel in the first row is adjacent to the first pixel in the second row.
 14. The method of claim 11 further comprising: capturing the first pixel value using at least the first pixel in the first row of the CCD, the first pixel in the second row of the CCD, a second pixel in the first row, and a second pixel in the second row.
 15. The method of claim 11 further comprising: capturing a second pixel value using at least a first pixel in a third row of the CCD and a first pixel in a fourth row of the CCD; wherein the first and the second rows are associated with a first color, and wherein the third and the fourth rows are associated with a second color.
 16. The method of claim 15 wherein the first color includes one of blue, green, and red, wherein the second color includes one of blue, green, and red, and wherein the first color differs from the second color.
 17. A scanning system comprising: a control unit; and a charge coupled device (CCD) comprising a first row comprising a first plurality of pixels and a second row adjacent to the first row and comprising a second plurality of pixels; wherein the control unit is configured to cause a first pixel value of an image to be captured using at least a first one of the first plurality of pixels and a first one of the second plurality of pixels.
 18. The scanning system of claim 17 wherein the first row is offset from the second row in a direction that is parallel to the first and second rows.
 19. The scanning system of claim 17 wherein the control unit is configured to cause the first pixel value of the image to be captured using at least the first one of the first plurality of pixels, the first one of the second plurality of pixels, a second one of the first plurality of pixels, and a second one of the second plurality of pixels.
 20. The scanning system of claim 17 wherein the CCD comprises a third row comprising a third plurality of pixels and a fourth row adjacent to the third row and comprising a fourth plurality of pixels, wherein the first and the second pluralities of pixels are associated with a first color, wherein the third and the fourth pluralities of pixels are associated with a second color, and wherein the control unit is configured to cause a second pixel value to be captured using at least one of the third plurality of pixels and one of the fourth plurality of pixels.
 21. The scanning system of claim 20 wherein the first color includes one of blue, green, and red, wherein the second color includes one of blue, green, and red, and wherein the first color differs from the second color.
 22. A system comprising: charge coupled device (CCD) means for sensing light comprising a first row comprising a first plurality of pixels associated with a first color, a second row adjacent to the first row and comprising a second plurality of pixels associated with the first color; and means for merging at least a first pixel value from a first one of the first plurality of pixels and a second pixel value from a first one of the second plurality of pixels to generate a first image value.
 23. The system of claim 22 wherein the first row is offset from the second row in a direction that is parallel to the first and second rows.
 24. The system of claim 22 further comprising: means for merging at least the first pixel value, the second pixel value, a third pixel value from a second one of the first plurality of pixels, and a fourth pixel value from a second one of the second plurality of pixels to generate the first image value.
 25. The system of claim 22 wherein the CCD means for sensing light comprises a third row comprising a third plurality of pixels associated with a second color and a fourth row adjacent to the third row and comprising a fourth plurality of pixels associated with the second color, and further comprising: means for merging at least a third pixel value from one of the third plurality of pixels and a fourth pixel value from one of the fourth plurality of pixels to generate a second image value.
 26. The system of claim 25 wherein the first color includes one of blue, green, and red, wherein the second color includes one of blue, green, and red, and wherein the first color differs from the second color.
 27. An apparatus comprising: a first register; a charge coupled device (CCD) comprising a first row comprising a first plurality of pixels, a second row adjacent to the first row and comprising a second plurality of pixels; and control logic configured to merge at least a first pixel value from a first one of the first plurality of pixels and a second pixel value from a first one of the second plurality of pixels into the first register.
 28. The apparatus of claim 27 wherein the first row is offset from the second row in a direction that is parallel to the first and second rows.
 29. The apparatus of claim 27 wherein the control logic is configured to merge at least the first pixel value, the second pixel value, a third pixel value from a second one of the first plurality of pixels, and a fourth pixel value from a second one of the second plurality of pixels into the first register.
 30. The apparatus of claim 27 further comprising: a second register; wherein the CCD comprises a third row comprising a third plurality of pixels and a fourth row adjacent to the third row and comprising a fourth plurality of pixels, wherein the first and the second pluralities of pixels are associated with a first color, wherein the third and the fourth pluralities of pixels are associated with a second color, and wherein the control logic is configured to merge at least a third pixel value from one of the third plurality of pixels and a fourth pixel value from one of the fourth plurality of pixels into the second register.
 31. The apparatus of claim 30 wherein the first color is selected from the group consisting of blue, green, and red, wherein the second color is selected from the group consisting of blue, green, and red, and wherein the first color differs from the second color.
 32. A program product comprising a computer-readable medium including instructions executable by a processor for: capturing a first pixel value using at least a first pixel in a first row of a charge coupled device (CCD) and a first pixel in a second row, adjacent to the first row, of the CCD.
 33. The program product of claim 32 wherein the first row is offset from the second row in a direction that is parallel to the first and second rows.
 34. The program product of claim 32 wherein the computer-readable medium includes instructions executable by the processor for: capturing the first pixel value using at least the first pixel in the first row of the CCD, the first pixel in the second row of the CCD, a second pixel in the first row, and a second pixel in the second row.
 35. The program product of claim 32 wherein the computer-readable medium includes instructions executable by the processor for: capturing a second pixel value using at least a pixel in a third row of the CCD and a pixel in a fourth row of the CCD; wherein the first row and the second row are associated with a first color, and wherein the third row and the fourth row are associated with a second color.
 36. The program product of claim 35 wherein the first color includes one of blue, green, and red, wherein the second color includes one of blue, green, and red, and wherein the first color differs from the second color. 